The present invention generally relates to a method of planarizing microstructures and, in particular, relates to one such method including the step of subjecting a microstructure having a planarization layer thereon to a plasma assisted chemical etching step.
During the present manufacture of microstructures, such as integrated circuits, it is customary to form a structure in, or on, a surface and subsequently, usually in anticipation of another fabrication step, form a plane layer of material over the structure so that the following fabrication step can be performed on a smooth flat surface. Further, the planarization layer of material serves as an electrical, and or thermal, insulation between the structures. Typically, the process can be repeated a number of times throughout the fabrication of an integrated circuit.
Currently, the final planarization step is performed by the physical and or chemical, polishing of a self-leveling coating. That is, the microstructure is covered by a planarization layer of material such that the microstructure is completely covered and the exposed surface of the material is relatively smooth. The planarization layer of material is then physically and/or chemically polished by use of conventional and commercially available equipment. This conventional method has numerous drawbacks. For example, the actual polishing, regardless of whether it is performed by physical polishing, conventional chemical etching or reactive ion etching, generally leaves defects in the surface of the self-leveling layer of material that reduce the accuracy of subsequent processing steps, thereby reducing the overall yield of the manufacturing process. Further, conventional chemical and mechanical techniques result in non-uniform thickness in the final film. In addition, particularly in the field of modem integrated circuit fabrication, these conventional processes can be a source of particulate contamination that can significantly reduce the yield of the integrated circuit manufacturing process. Clearly, the common detraction of conventional polishing processes is that physical contact with the self-leveling material is required. Further, the material of the self-leveling layer must be chosen with great care to ensure its compatibility with the requisite temperatures and materials to which it is exposed during the subsequent processes.
Hence, a method of planarizing microstructures that is accurate and clean is highly desirable in the general industry of microstructures and extremely desirable in the particular field of integrated circuit and semiconductor manufacturing.